1. Field of the Invention
The present invention relates to a memory device. In particular, the present invention provides a transistor for a semiconductor device and a method of forming the same, and more specifically to a transistor for a semiconductor device and a method of forming the same wherein a sufficient channel area of a transistor for a semiconductor device is secured in spite of reduction of design rules according to a high integration of a semiconductor device, thereby securing drive current for the transistor.
2. Discussion of the Related Art
Recently, there has been a trend in designing lower power transistors for a semiconductor device securing operation current even though design rules of the semiconductor device are reduced. Channel area is one considerable factor for determining drive current in a cell transistor for a semiconductor device.
In a conventional plane channel transistor, it is difficult for a transistor having a channel dimension of 1000 nm or less to secure On/Off characteristics of the transistor. Typically, a fin-FET transistor protruding out of a channel region is employed as a cell transistor having design rules of 50 nm or less, thereby securing sufficient drive current of the transistor.
FIG. 1 is a simplified layout view illustrating an active region 1, a device isolation region 3, and a gate region 5 in accordance with a conventional transistor for a semiconductor device. FIGS. 2 through 5 are simplified cross-sectional views illustrating a method of forming a transistor for a semiconductor device in accordance with the conventional transistor. FIGS. 2 and 4 are cross-sectional views taken along the line I-I′, FIG. 3 is a cross-sectional view taken along the line II-II′ in FIG. 1, and FIG. 5 is an enlarged view of III in FIG. 4.
Referring to FIGS. 2 and 3, a pad insulating film pattern (not shown) defining a device isolation region 3 shown in FIG. 3 is formed on a semiconductor substrate 10. The semiconductor substrate 10 is etched using the pad insulating film pattern as an etching mask by such a predetermined thickness so as to form a trench 13 for device isolation. Thereafter, an oxide film 15 and a nitride film 17 having a predetermined thickness are successively formed on the surface of the trench 13, and then a device isolation film 20 filling the trench 13 is formed. Next, the device isolation film 20, the nitride film 17 and the oxide film 15 in the gate region 5 shown in FIG. 1 are etched using a recess gate region mask (not shown) as an etching mask by such a predetermined thickness so as to form a recess gate region 25 exposing a sidewall of a fin-type active region 1, wherein the recess gate region mask is overlapped with the gate region 1. After that, the remaining pad insulating film pattern is removed to expose the active region 1.
Referring to FIG. 4, a channel ion implantation process is performed on the exposed active region 1. Next, a gate oxide film 30 is formed on the entire surface of the exposed active region 1, and then a gate structure 40 filling the recess gate region 25 is formed in the gate region 5 shown in FIG. 1.
Referring to FIG. 5, a channel region of the fin-type gate structure 40 is formed on a sidewall and an upper portion of the protruded fin-type active region, so that the channel length of the fin-type gate structure 40 is increased as compared to that of the plane channel transistor. Since a depletion layer region 45 of a cell transistor is limited to the width of the active region, the fin-type gate structure has lowered threshold voltage thereof.
In fabricating a transistor for a semiconductor device in design rules of 50 nm or less, a phenomenon occurs in which a width of a depletion layer region in a channel region becomes larger than a half width of a fin-type channel region. Due to this phenomenon, it is essential to decrease the threshold voltage of the transistor. Accordingly, in order to satisfy the regulated threshold voltage of the transistor, the transistor must have a highly concentrated ion implantation channel region. However, the highly concentrated ion implantation channel region causes an increase in junction leakage current, thereby degenerating refresh characteristics of DRAM.